1. Field of the Invention
The present invention relates to a semiconductor device such as a memory, a photoelectric converter device, a signal processing device or the like, for use in various electric appliances, and a method for producing the same.
2. Related Background Art
In recent efforts toward attaining the higher level of device integration, there has been a desire for the development of miniaturized functional devices such as a MOS transistor with submicron gate length. On the other hand, an improvement in the voltage resistance characteristics is desired, as such miniaturization tends to cause concentration of the electric field in the vicinity of the drain. In order to prevent the avalanche breakdown in the vicinity of the drain when a high voltage is applied thereto, there has been employed a light doped drain (LDD) structure, in which a drain area of a low doping concentration is formed adjacent to the drain area, thereby relaxing the electric field around the drain.
FIGS. 1A to 1C schematically illustrate the conventional process for forming the drain area of low doping concentration. At first, as shown in FIG. 1A, a gate insulation film 2 is formed on a silicon substrate 1, then a polycrystalline silicon gate film 3 and a photoresist layer 4 are patterned, and phosphorus is implanted with a high concentration, utilizing the photoresist 4 as a mask.
Then as shown in FIG. 1B, a photoresist pattern 5 is formed, and phosphorus is implanted with a low concentration, utilizing said photoresist 5 as a mask. Finally, as shown in FIG. 1C, an intermediate insulation film 6 is formed by an ordinary method, and an annealing treatment is applied. There are thus conducted formation of a source area 7, a high-concentration drain area 8, a low-concentration drain area 9, a channel area 10 and electrodes 11.
In the above explained conventional example, however, the low-concentration drain area 9 is formed, after the impurity implantation into the silicon substrate 1 through the photoresist mask for forming the drain area 8, by implanting an impurity of the same conductive type as that of the drain area 8 into an area of the silicon substrate 1 between the drain area 8 and the channel area 10. Consequently, depending on the accuracy of alignment, the width of said low-concentration drain area 9, present between the channel area 10 and the drain area 8, fluctuates inevitably, so that a fluctuation in the drain voltage resistance has been unavoidable, as will be explained later.
FIGS. 2A and 2B show the relationship between the offset and the drain voltage resistance, wherein the offset L1 is, as shown in FIG. 2A, the distance from a lateral wall of a gate 3 to the boundary between the low-concentration drain area 9 and the high-concentration drain area 8. As shown in FIG. 2B, the drain voltage resistance increases linearly with said offset L1. In the conventional process, the standard deviation of the precision of alignment is 0.3 .mu.m. Consequently the offset L1 inevitably involves a fluctuation of 0.3 .mu.m, which brings about a fluctuation of about 5 V in the drain voltage resistance.
On the other hand, for reducing the signal delay time, it has been proposed to form the gate electrode and its wiring with silicide (silicon metal alloy) or with a polycide structure (laminate structure of polycrystalline silicon and silicide film) thereby reducing the specific resistivities thereof.
However, such silicide or polycide structure of the gate for achieving a high speed still requires improvements in the following areas, in order to achieve production of the currently required miniaturized semiconductor devices of high-speed function with a high production yield. More specifically, the conventional silicide structure has been associated with the following drawbacks:
(1) that the threshold voltage (V.sub.th) of the MOS device varies depending on the work function of the silicide; and PA0 (2) that a metal from the silicide diffuses into the gate oxide film 5, thereby deteriorating the MOS transistor. PA0 (3) that the specific resistivity can only be reduced to ca. 3 .OMEGA./.quadrature.; and PA0 (4) that an insulation film or a precipitated impurity film, if present at the interface between the polycrystalline silicon and silicide, may result in a significant deterioration of the gate voltage resistance or a peeling of the silicide film, called pest phenomenon.
On the other hand, the polycide structure has also been associated with the following drawbacks: